1. Field of the Invention
The present invention relates to a metal nitride film, a semiconductor device using the metal nitride film and the manufacturing method of the semiconductor device, more particularly to a metal nitride film usable for metal gate electrodes, a semiconductor device having a high permittivity insulating film and a metal nitride film as a metal gate electrode, and the manufacturing method of the semiconductor device. Moreover, the present invention relates to a technology for attaining high performance of semiconductor devices, for example, such as MOSFETs (Metal Oxide Semiconductor Field Transistor).
2. Description of the Related Art
In the leading-edge CMOS (complementary MOS) device development, in which the miniaturization of transistors advances, there are such problems as the deterioration of drive current due to the depletion of a polysilicon (Poly-Si) electrode, and the increase in gate current due to thinning in a gate insulating film. Accordingly, a composite technology is examined, in which a metal gate is applied to avoid the depletion of the electrode, and, at the same time, gate leak current is reduced by thickening a physical film thickness using a high permittivity material as the gate insulating film. As the material for use in the metal gate electrode, pure metals, metal nitrides, silicide materials, etc. are examined, wherein, in all cases, the threshold voltage (Vth) of N-type MOSFETs and P-type MOSFETs must be able to be set to a suitable value. When a conventional gate electrode via a polycrystalline silicon film is used, the threshold voltage of the transistor is determined by the impurity concentration in the channel region and the impurity concentration in the polycrystalline silicon film. On the other hand, when the metal gate electrode is used, the threshold voltage of the transistor is determined by the impurity concentration in the channel region and the work function of the gate electrode. In order to actualize a Vth of ±0.5 V or less in CMOS transistors, for N-type MOSFETs, it is necessary to use a material having a work function of the Si mid gap (4.6 eV) or less, desirably 4.4 eV or less. On the other hand, for P-type MOSFETs, it is necessary to use a material having the work function of the Si mid gap (4.6 eV) or more, desirably 4.8 eV or more as the gate electrode.
As a means for realizing these, a Metal-inserted Poly-silicon Stack (MIPS) having a high consistency with existing CMOS production processes is examined. In the method, a gate electrode having a metal film inserted between Poly-Si and the gate insulating film is formed, and the threshold voltage is adjusted by the work function of the inserted gate electrode. At this time, there is such a problem that the work function of the metal film varies by the cross reaction with the gate insulating film or the poly-silicon in a heat treating process.
For example, Japanese Patent Application Laid-open Publication No. 2008-16538 discloses a method using a gate electrode including a laminate structure of polycristalline silicon, PVD-TiN (second metal layer) and CVD-TiN (first metal layer). It describes that the method can actualize TiN having a work function of 4.8 eV or more that is suitable for the metal gate of P-type MOSFETs by forming TiN being the first metal layer by a thermal CVD method using TiCl4 and NH3 at a low temperature of 450° C. or less. Moreover, it describes that TiN oriented toward a (100) plane is formed by forming TiN being the second metal layer at 500° C. (a temperature higher than that for forming TiN of the first metal layer) by a PVD method. There is such description that the TiN oriented toward a (100) plane has an effect of suppressing the lowering of the work function due to the diffusion of Si from Poly-Si to TiN in a thermal process (for example, an activation annealing process) after forming the gate electrode.
Japanese Patent Application Laid-open Publication No. 2009-099747 discloses a technology that applies WSi and TiAlN as the gate electrode of a P-type channel MOSFET. There is such description that, according to the method, TiAlN generates phase separation into TiN and AlN by performing a high temperature heat treatment because TiAlN has a poor heat resistance, and that, at this time, excessive Al diffuses into the gate insulating film through the WSi film and a dipole having an Al—O bond is formed in the gate insulating film to obtain a high work function of 4.8 eV or more.
Furthermore, Japanese Patent Application Laid-open Publication No. 2009-141040 discloses a technology applying a TiAlN film as the gate electrode of a P-type channel MOSFET. There is such description that the method can obtain a high work function of 4.8 eV or more by depositing a TiAlN film containing an Al element from 10% to 50% in a cation ratio as the gate electrode and, after that, performing a heat treatment for diffusing the Al element into the gate insulating film, based on the same phenomenon as that in Patent Document 2.
There are, however, following problems in the above-described technologies, respectively.
The technology described in Japanese Patent Application Laid-open Publication No. 2008-16538 is an effective technology in terms of realizing TiN having a high work function, and being capable of suppressing the lowering of the work function due to the diffusion of Si from Poly-Si into TiN in a thermal process after the formation of the gate electrode. In the method described in Japanese Patent Application Laid-open Publication No. 2008-16538, however, there is such a problem that the number of processes for producing the gate electrode increases because TiN having a high work function is formed by a CVD method, and then TiN capable of suppressing the diffusion of Si is formed by a PVD method. Moreover, there is such a problem in the formation method of a TiN film by a CVD method using NH3 as a raw gas that the threshold voltage varies because an oxygen hole is formed in the gate insulating film by the reduction action by NH3.
The methods described in Japanese Patent Application Laid-open Publication No. 2009-099747 and Japanese Patent Application Laid-open Publication No. 2009-141040 are technologies, of course, that are effective for obtaining a high work function. But, according to the methods described in Japanese Patent Application Laid-open Publication No. 2009-099747 and Japanese Patent Application Laid-open Publication No. 2009-141040, there occurs such a problem that EOT (Equivalent Oxide Thickness) (film thickness in terms of the oxide film) varies because an effective work function is controlled by the diffusion of Al into the gate insulating film. Moreover, there is such a problem that these methods do not describe a film composition optimal for a high permittivity gate insulating film or a formation method thereof.
The method described in Japanese Patent Application Laid-open Publication No. 2008-16538 is an effective technology, of course, capable of controlling the work function by the concentration of nitrogen contained in titanium nitride. But, there is such a problem that since the method described in Japanese Patent Application Laid-open Publication No. 2008-16538 uses a silicon nitride film or a silicon nitride oxide film as the gate insulating film, it does not describe the film composition or crystal orientation of a TiN film optimal for a high permittivity gate insulating film.
Furthermore, there is such a problem that the controlling method of the crystal orientation of a TiN film described in Japanese Patent Application Laid-open Publication No. 2009-099747 describes nothing about a film composition for obtaining the optimal work function.